This application relies for priority upon Korean Patent Application No. 2000-01549, filed on Jan. 13, 2000, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor DRAM (dynamic random access memory) device with uniquely shaped storage nodes resulting in increased surface area and increased capacitance for a memory cell.
2. Description of the Related Art
Advances in the scaling-down of integrated circuit devices have led to smaller wafer areas and consequently smaller devices. High density DRAM (dynamic random access memory) devices, for example, leave little room for the storage node of a memory cell. As is well known, a unit cell of the DRAM comprises one transistor and one cell capacitor to store information. The information storage capacity of the capacitor is proportional to the capacitance, and the capacitance must be maintained at a minimum acceptable level to ensure improved read/write operation and to reduce soft error rates.
However, as the footprint (i.e., the area of a silicon wafer allotted individual memory cells) shrinks, the area occupied by the capacitor must also be reduced. This in turn reduces the surface area of the capacitor electrode, thereby reducing capacitance. This is because cell capacitance (C) is equal to k (A/d), where k is the dielectric constant of the capacitor dielectric, A is the electrode area and d represents the spacing between the electrodes (thickness of the dielectric film).
Accordingly, several techniques have been developed to increase the overall capacitance of the cell capacitor without significantly affecting the wafer area occupied by the cell. One technique is to increase the surface area of the electrode. For example, trench type, stack type and cylindrical type electrode structures have been fabricated.
FIG. 1 is a top plan view schematically showing a conventional cylindrical capacitor. Referring to FIG. 1, a unit cell region 100 is arranged repeatedly lengthwise and widthwise (longitudinally and laterally) with spacing xe2x80x9ccxe2x80x9d between adjacent unit cell regions 100, to form a cell array region of the DRAM cell. One cylindrical capacitor 120 is oriented within the unit cell region 100 so as to substantially occupy most of the unit cell region. The spacing between the capacitors 120 (e.g., spacing between adjacent unit cells) is still denoted by xe2x80x9ccxe2x80x9d.
Because of the downward trend in cell size, the area occupied by the cylindrical capacitor is being decreased in a given area (i.e., unit cell area is being decreased), thereby the top surface area thereof also decreases. To compensate for the decrease in the top surface area, the height of the cylindrical capacitor can be increased so as to increase the sidewall surface area. However, several problems arise when trying to increase the height of the cylindrical capacitor, as described below with regard to FIGS. 2 and 3.
FIG. 2A is a plan view of a pair of conventional cylindrical capacitors; FIG. 2B is a perspective view of the conventional capacitors of FIG. 2A; and FIG. 3 is a side cross-sectional view showing conventional cylindrical storage nodes.
The capacitor as shown in FIGS. 2A, 2B and 3 is formed through the following steps. A contact plug 110 is formed in an insulating layer formed on a semiconductor substrate. A storage electrode 120 is formed on the insulating layer to be electrically connected to the contact plug 110. A plate electrode 130 is formed over the storage electrode 120 with an interposing dielectric layer (not shown) therebetween. An interlayer insulating layer 140 is formed over the entire surface of the substrate. If the height h (see FIG. 2B) of the capacitor electrode 120 is increased for the purpose of increasing the side surface area of the capacitor, the height difference between cell array region (A), where the capacitor is formed, and peripheral region (B), where the capacitor is not formed, is also increased. In other words, a step is generated between the cell array region and the peripheral region as shown in FIG. 3. Also, when a BPSG (borophosphosilicateglass) layer is used as the interlayer insulating layer 140, the re-flow process for BPSG planarization may cause the storage electrode 120 to tilt or move (see FIG. 3), which degrades the contact between the storage electrode 120 and the contact plug 110.
FIGS. 2A and 2B show respective top plan and perspective views of a pair of conventional cylindrical storage nodes with a rectangular configuration. As compared to FIG. 1, when the top surface of the cylindrical storage electrode exhibits a rectangular configuration (i.e., when the storage electrode occupies nearly the whole area of the rectangular unit cell region), the maximum top surface and side surface area can be obtained.
Although the rectangular storage electrode of FIGS. 2A and 2B occupies more area than the elliptical storage electrode of FIG. 1, there is still a need for a capacitor that exhibits more surface area than the rectangular storage electrode.
The present invention solves one or more of the above-mentioned problems and it is an object of the present invention to provide a DRAM device with increased surface area.
In accordance with the present invention, the DRAM device comprises a pair of cells arranged lengthwise and widthwise to form a cell array region of a semiconductor substrate. Two transistors in the pair of cells share a common drain region formed in the substrate between gates electrodes of each transistor, and two storage nodes in the pair of cells are electrically connected to each source of the two transistors, respectively. One storage node in the pair of cells is an xe2x80x9cLxe2x80x9d shaped pole and the other is a xe2x80x9creversed Lxe2x80x9d shaped pole, rotated 180 degree with respect to the one storage node. Each storage node can be divided into two parts. One is main body pole and the other is protruding pole. The protruding pole protrudes from a side wall of the main body pole.
More particularly, each main body pole is electrically connected to each source of the two transistors, respectively, through a storage node contact plug, and the main body pole occupies most of the cell. Each protruding pole in the pair of cells protrudes into a part of the adjacent cell respectively. A top surface of the main body pole and the protruding pole has a rectangular configuration. A top surface area of the protruding pole is at most half of the main body pole. A spacing between the two storage nodes is the same dimension as the shorter width of the protruding pole. The longer width of the protruding pole is the same dimension as the shorter width of the main body pole plus the spacing between the two storage nodes.